blocking & non-bloking assignment in verilog

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ravi vadi
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Joined: Tue Jul 22, 2014 6:09 pm

blocking & non-bloking assignment in verilog

Postby ravi vadi » Thu Jul 24, 2014 6:12 am

what is the differnce between blocking & non-blocking assignment in verilog?
what is the importance of that?
how it is simulate?


Re: blocking & non-bloking assignment in verilog

Postby Guest » Fri Jun 19, 2015 8:32 pm

Blocking Statements: A blocking statement must be executed before the execution of the statements that follow it in a sequential block. In the example below the first time statement to get executed is a = b followed by

Nonblocking Statements: Nonblocking statements allow you to schedule assignments without blocking the procedural flow. You can use the nonblocking procedural statement whenever you want to make several register assignments within the same time step without regard to order or dependence upon each other. It means that nonblocking statements resemble actual hardware more than blocking assignments.


Re: blocking & non-bloking assignment in verilog

Postby Guest » Fri Jun 19, 2015 8:33 pm

The blocking vs non-blocking is so that your gate level (synthesis) matches your RTL simulation. Using a different one to alter the behaviour of the simulation as far as I know will not effect synthesis and therefore the behaviour of gate-level.

<= non-blocking effectively take a temporary copy of the copy right-hand side, and make the = blocking assignment at the end of the timestep.
a <= b;
b <= a;

is equivalent to:
a_temp = b;
b_temp = a;
a = a_temp;
b = b_temp;

The example uses combinatorial logic, that is it contains no state, so all inputs must be defined by all outputs.
always@* begin
iowrb_int <= iowrb_met;
iordb_int <= iordb_met;
iowrb_met <= iowr_bar;
iordb_met <= iord_bar;

When the right hand side updates the block should be retriggered. Since iowrb_met is on both sides I am not sure what this implies interms of electrical connectivity.

while <= implies copying to a temp location, combinatorial logic does not have this capability, it is always and continuously driven by the assignment.

I think in simulation you effectively have this:
always@* begin
iowrb_int_temp = iowrb_met;
iordb_int_temp = iordb_met;
iowrb_met = iowr_bar;
iordb_met = iord_bar;
iowrb_int = iowrb_int_temp;
iordb_int = iordb_int_temp;

In hardware you would have:
always@* begin
iowrb_int = iowrb_met; //= iowr_bar;
iordb_int = iordb_met; //= iord_bar;
iowrb_met = iowr_bar;
iordb_met = iord_bar;

Where iowrb_int is effectively the same as iowrb_met

Flip-flops are implied using always @(posedge clk
Combinatorial logic is implied using always @* but latches can be implied when the output is not fully defined from inputs.

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